Principal Product Application Engineer - Leo

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Principal Product Application Engineer - Leo in USA

Astera Labs
Full time
Email

USA
09/30/2026
Report

San Jose, CA

Responsibilities

Lead customer engagements for Leo CXL Smart Memory Controllers, including firmware bring-up, feature enablement, and issue triage.
Develop, validate, and debug C and Python firmware, test scripts, automation frameworks, and diagnostic tools.
Drive requirements and technical discussions for DDR4/DDR5 interfaces, initialization, training, RAS features, and performance tuning.
Serve as the primary firmware technical contact for hyperscaler and OEM accounts and drive issue resolution and feature demonstrations.
Implement CXL, PCIe, and JEDEC DDR specification requirements in firmware solutions.
Collaborate with firmware, hardware, systems, and product management teams on firmware releases and customer collateral.
Create application notes, release notes, design guides, and other customer-facing documentation.
Represent the Leo team in customer technical reviews, design-in engagements, and industry forums.

Requirements

Bachelor’s degree in Electrical Engineering, Computer Science, or a related technical field is required; a master’s degree is preferred.
8+ years of experience in firmware development, product applications engineering, or a related role supporting complex SoC or silicon products for server, storage, or networking applications.
High proficiency in C for embedded firmware development in RTOS environments.
Working knowledge of CXL 1.1, 2.0, or 3.0, including memory expansion, pooling, and sharing.
Proficiency in Python for scripting, test automation, and diagnostic tooling.
Deep hands-on knowledge of DDR4 and/or DDR5 DRAM interfaces, including initialization, training algorithms, timing margins, and ECC/RAS features.
Experience bringing up, debugging, and validating memory or I/O subsystems on server platforms.
Strong debugging and root-cause analysis skills for complex embedded systems.
Familiarity with SoC interfaces including DDR controllers, PCIe controllers, and on-chip memory subsystems.
Experience with SCM, preferably Git, code reviews, and CI/CD pipelines.
Preferred experience includes PCIe endpoint firmware, PCIe protocol layers and enumeration, MSI/MSI-X, SR-IOV, error handling, PCIe/CXL protocol analyzers, BERT, and lab debug equipment.
Preferred experience includes BIOS/BMC/OS interactions with PCIe/CXL devices, MMIO/RAS concepts, server memory performance tuning, and customer-facing or field applications work in semiconductor or systems companies.
Must be authorized to work in the US and available to start immediately.

Benefits

The position is required onsite in San Jose, California.
The role offers the opportunity to work directly with hyperscalers and OEM partners on complex AI infrastructure and semiconductor products.

Salary: $175k - $230k/yr

Astera Labs

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform int...

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